EVAL-CONTROLBRD22【PDF 10/18 页】Differential Input, Dual 2 MSPS, 12-Bit,

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AD7322

Preliminary Technical Data

When the ADC starts a conversion (

and SW1 will move to position B, causing the comparator to

become unbalanced. The control logic and the charge

redistribution DAC is used to add and subtract fixed amounts

of charge from the sampling capacitor arrays to bring the

comparator back into a balanced condition. When the

comparator is rebalanced, the conversion is complete. The

Control Logic generates the ADC output code.

), SW2 will open

Figure 5

Figure 5. ADC Conversion Phase(Single Ended)

Figure 6

Acquisition phase. For the Conversion Phase, SW3 will open,

SW1 and SW2 will move to position B, see

impedances of the source driving the Vin+ and Vin- pins must

be matched; otherwise the two inputs will have different settling

times, resulting in errors.

Figure 6. ADC Differential Configuration during Acquisition Phase

shows the differential configuration during the

. The output

Figure 7

Figure 7. ADC Differential Configuration during Conversion Phase

Output Coding

The AD7322 default output coding is set to two’s complement.

The output coding is controlled by the Coding bit in the

Control Register. To change the output coding to Straight

Binary Coding the Coding bit in the Control Register must be

set. When operating in Sequence mode the output coding for

each channel in the sequence will be the value written to the

coding bit during the last write to the Control Register.

Transfer Functions

The designed code transitions occur at successive integer LSB

values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is dependant

on the Analog input Range selected.

Table 6. LSB sizes for each Analog Input Range

Input Range

Full Scale Range/4096

LSB Size

±10V

20V/4096

4.882 mV

±5V

10V/4096

2.441 mV

±2.5V

5V/4096

1.22 mV

0 to 10V

10V/4096

2.441 mV

The ideal transfer characteristic for the AD7322 when Twos

Complement coding is selected is shown in

ideal transfer characteristic for the AD7322 when Straight

Binary coding is selected is shown in

, and the

Figure 8

Figure 8. Twos Complement Transfer Characteristic (Bipolar Ranges)

Figure 9

Figure 9. Straight Binary Transfer Characteristic (Bipolar Ranges)

000...000

111...111

FSR/2 + 1LSB

ANALOG INPUT

011...111

011...110

100...001

100...000

100...010

000...001

+FSR/2 - 1LSB

VREF - 1LSB

000...000

-FSR/2

ANALOG INPUT

111...111

111...110

000...001

000...010

111...000

011...111

1LSB

FSR/2 -1LSB

ANALOG INPUT

The analog inputs of the AD7322 may be configured as Single-

Ended, True differential or Pseudo Differential via the Control

The AD7322 can accept True bipolar input signals. On power

up the Analog inputs will operate as 2 Single-Ended Analog

Input Channels. If True Differential or Pseudo Differential is

required, a write to the Control register is necessary to change

this configuration after power up.

of the Register Section.

Table 9

Figure 10 shows the equivalent Analog input circuit of the

AD7322 in Single-Ended Mode.

Analog input structure in Differential mode. The Two Diodes

provide ESD protection for the Analog Inputs.

shows the equivalent

Figure 11

Rev. PrE | Page 10 of 18

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